TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2824304
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2834394
Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2864251
Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2855145
Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2864263
Security Assessment of Micro-Electrode-Dot-Array Biochips
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2864249
A Versatile Pulse Control Method to Generate Arbitrary Multidirection Multibutterfly Chaotic Attractors
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2855121
IC Protection Against JTAG-Based Attacks
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2802866
Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2801228
Design Space Exploration of Neural Network Activation Function Circuits
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2871198
New 3-D CMOS Fabric With Stacked Horizontal Nanowires
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2848588
Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878183
A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2818707
On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2864246
Single-Layer GNR Routing for Minimization of Bending Delay
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878164
A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2821442
Formal Probabilistic Analysis of Low Latency Approximate Adders
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2803622
A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2821559
DtCraft: A High-Performance Distributed Execution Engine at Scale
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2834422
Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2801244
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2834424
Collaborative Power Management Through Knowledge Sharing Among Multiple Devices
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2837131
Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878159
Built-In Test for Hidden Delay Faults
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2864255
Alleviating Hot Data Write Back Effect for Shingled Magnetic Recording Storage Systems
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878190
Improving Flash Memory Performance and Reliability for Smartphones With I/O Deduplication
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2834395
Bug Prediction of SystemC Models Using Machine Learning
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878193
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2818689
Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2859266
Optimal Performance-Aware Cooling on Enterprise Servers
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2855122
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2846631
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2821563
Scalable Construction of Clock Trees With Useful Skew and High Timing Quality
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2834437
Obfuscated Built-In Self-Authentication With Secure and Efficient Wire-Lifting
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2877012
Game Theoretic Feedback Control for Reliability Enhancement of EtherCAT-Based Networked Systems
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2859241
An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2818725
A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2846634
A Sufficient Response Time Analysis Considering Angular Phases Between Rate-Dependent Tasks
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878163
Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2855131
Reliability Analysis of Mixture Preparation Using Digital Microfluidic Biochips
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2819081
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878166
Enhanced Phase-Driven $Q$ -Learning-Based DRM for Multicore Processors
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2877014
Multi-Pair Active Shielding for Security IC Protection
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878175
Table-Based Model of a Dual-Gate Transistor for Statistical Circuit Simulation
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2852756
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2818688
Verification at RTL Using Separation of Design Concerns
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2848589
Comprehensive Side-Channel Power Analysis of XTS-AES
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2878171
On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2803621
A Cross-Layer Framework for Temporal Power and Supply Noise Prediction
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2871820
DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography
来源期刊:IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDOI:10.1109/TCAD.2018.2812122