IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING

A Novel DBSCAN-Based Defect Pattern Detection and Classification Framework for Wafer Bin Map

Improved Normalized Cross-Correlation for Defect Detection in Printed-Circuit Boards

Fault Detection Strategy Based on Weighted Distance of $k$ Nearest Neighbors for Semiconductor Manufacturing Processes

Nanoscale Metrology of Line Patterns on Semiconductor by Continuous Wave Terahertz Multispectral Reconstructive 3-D Imaging Overcoming the Abbe Diffraction Limit

Enhanced Stacked Denoising Autoencoder-Based Feature Learning for Recognition of Wafer Map Defects

Feature Extraction From Analog Wafermaps: A Comparison of Classical Image Processing and a Deep Generative Model

Wafer Defect Pattern Recognition and Analysis Based on Convolutional Neural Network

Denoised Residual Trace Analysis for Monitoring Semiconductor Process Faults

The Design and Implementation of an Embedded Real-Time Automated IC Marking Inspection System

Development of Novel Solar Cell Micro Crack Detection Technique

CMOS-Compatible MESFETs for High Power RF Integrated Circuits

Statistical Process Control for Monitoring the Particles With Excess Zero Counts in Semiconductor Manufacturing

A Wafer Map Yield Prediction Based on Machine Learning for Productivity Enhancement

A Condition Change Detection Method for Solar Conversion Efficiency in Solar Cell Manufacturing Processes

A 0.18- $\\mu$ m LDMOS With Excellent Ronsp and Uniformity by Optimized Manufacture Process

A Novel Method for Deposit Accumulation Assessment in Dry Etching Chamber

Sub-Resolution Assist Feature Cleanup Based on Grayscale Map

Strategies for Reducing Particle Defects in Ti and TiN Thin-Film Deposition Processes

Mechanism and Control Technique of Wafer Warpage in Process Integration for Trench Field Plate Power MOSFET

Displaying Data Effectively Using an Automated Process Dashboard

Advanced Process Control Using Virtual Metrology to Cope With Etcher Condition Change

Marker Layout for Optimizing the Overlay Alignment in a Photolithography Process

Modeling Spin Coating Over Topography and Uniformity Improvements Through Fill Patterns for Advanced Packaging Technologies

Virtual Metrology Model Robustness Against Chamber Condition Variation Using Deep Learning

Reduced Contact Resistance in GaN Using Selective Area Si Ion Implantation

Novel Volatile Film for the Protection of Organo-Silicate Glass Dielectric Materials

Photoluminescence Imaging for Buried Defects Detection in Silicon: Assessment and Use-Cases

A Productivity-Oriented Wafer Map Optimization Using Yield Model Based on Machine Learning

${K}$ -Cyclic Schedules and the Worst-Case Wafer Delay in a Dual-Armed Cluster Tool

Guest Editorial Special Section on the 2018 International Symposium on Semiconductor Manufacturing

Research Into the LSTM Neural Network-Based Crystal Growth Process Model Identification

Modelling and Control of Backside-Induced ESD Defects During Wet-Chemical Processes in GaAs Front End Manufacturing

Characterization of Electroless Nickel Plated Materials During High Temperature Solder Processing

Bessel Decomposition of Temperature Profiles in Film Deposition Reactors

Incorporating Virtual Metrology Into Failure Prediction

The Long Journey From Standardization to Fully Fab Automation and More

Characterization of New Method for CMP Dresser to Saving Ultrapure Water Consumption

Gross Die Per Wafer and Yield Optimization for GaAs ICs With Sub-Micron Features

Scribe Line Defect-Induced Yield Loss in FINFET Technology

Spatial Correlated Data Monitoring in Semiconductor Manufacturing Using Gaussian Process Model

A Comprehensive Investigation of Depth Filter Functionality for a Colloidal Silica Slurry Used for Semiconductor Manufacturing Process

Special Section on the 2017 SEMI Advanced Semiconductor Manufacturing Conference

Editorial 2018 Best Paper Award

Fluid Dynamic Modeling and Flow Visualization of an Industrial Wet Chemical Process Bath

Design and Development of InP DHBTs With High Breakdown Voltage for Ka-Band PA Applications

In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers

Modeling and Controlling Layout Dependent Variations in Semi-Additive Copper Electrochemical Plating